Fast Power and Energy Efficiency Analysis of FPGA-based Wireless Base-band Processing

Nowadays, demands for high performance keep on increasing in the wireless communication domain. This leads to a consistent rise of the complexity and designing such systems has become a challenging task. In this context, energy efficiency is considered as a key topic, especially for embedded systems in which design space is often very constrained. In this paper, a fast and accurate power estimation approach for FPGA-based hardware systems is applied to a typical wireless communication system. It aims at providing power estimates of complete systems prior to their implementations. This is made possible by using a dedicated library of high-level models that are representative of hardware IPs. Based on high-level simulations, design space exploration is made a lot faster and easier. The definition of a scenario and the monitoring of IP's time-activities facilitate the comparison of several domain-specific systems. The proposed approach and its benefits are demonstrated through a typical use case in the wireless communication domain.Comment: Presented at HIP3ES, 201

Dynamic Power Evaluation of LTE Wireless Baseband Processing on FPGA

International audienceMobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for FPGA-based systems is presented. It aims at providing accurate and fast power estimations of an entire system prior to its implementation. It also aims at making design space exploration easier. We introduce an innovative scenario-level in order to facilitate the comparison of domain-specific systems. We show the effectiveness of our approach on several LTE baseband configurations which leads to a low absolute error, compared to classic estimations. It also exhibits a high speed-up factor which is determinant during design space exploration. I. INTRODUCTION Today, the data traffic that is generated on mobile networks continues to grow rapidly. According to [1], global mobile data increases of 69% in 2014 and it will have a compound annual growth rate of 57% from 2014 to 2019. To deal with these issues, mobile networks and user equipments tend to constantly adapt their processing capabilities. Among all possible solutions, a popular example is the LTE standard. The complexity of systems like LTE makes their design and development a challenging task, especially when they are implemented in embedded systems in which specific constraints have to be taken into account (power, size, performance , etc.). The number of parameters that can have an impact over power consumption makes the power estimation even more difficult. As the new technologies clearly enhance the performance in terms of throughput, QoS, it also implies a higher power consumption and more heat dissipation. One of the most popular families of digital circuits in embedded systems are the Field Programmable Gate Arrays (FPGA). These devices represent an attractive technology and make it possible to implement complex systems due to their high density of gates and heterogeneous resources. As compare to ASIC that can achieve better performance [2], FPGAs offer more flexibility. FPGA-based systems can be made of IP (Intellectual Property) which are hardware cores that facilitate design reuse and speed up development time. Their power consumption is generally divided into static and dynamic power. Static power comes from leakage currents whereas dynamic power is generated by the transistors switching activity as soon as the circuit is active

Radar for Assisted Living in the Context of Internet of Things for Health and Beyond

This paper discusses the place of radar for assisted living in the context of IoT for Health and beyond. First, the context of assisted living and the urgency to address the problem is described. The second part gives a literature review of existing sensing modalities for assisted living and explains why radar is an upcoming preferred modality to address this issue. The third section presents developments in machine learning that helps improve performances in classification especially with deep learning with a reflection on lessons learned from it. The fourth section introduces recent published work from our research group in the area that shows promise with multimodal sensor fusion for classification and long short-term memory applied to early stages in the radar signal processing chain. Finally, we conclude with open challenges still to be addressed in the area and open to future research directions in animal welfare

Dynamic Power Estimation of FPGA-based Wireless Communication Systems

The growing complexity of current and future wireless communication systems makes power estimation a challenging task for designers. Nowadays, it is required to estimate power very fast in order to explore and validate design choices as soon as possible in the design flow. In this paper, we propose a new dynamic power estimation methodology for FPGA-based systems. Our methodology aims to provide accurate and fast power estimations of an entire system prior to any implementation. It also aims at making design space exploration easier. We introduce a scenario-level in order to facilitate the comparison of domain-specific algorithms. This methodology relies on an IP power characterisation phase and a behavioural simulation of the modeled system using SystemC. We show the effectiveness of our approach on typical wireless communication systems which leads to a maximum absolute error lower than 6% compared to classic estimations

Elderly care: activities of daily living classification with an S band radar

Falls in the elderly represent a serious challenge for the global population. To address it, monitoring of daily living has been suggested, with radar emerging to be a useful platform for it due to its various benefits with acceptance and privacy. Here, we show results from the use of an S band radar for activity detection and the importance of selecting specific frequency bins to improve its suitability for human movement classification. The use of feature selection to improve detection of key activities such as falls has been presented. Initial results of 65% are improved to 85% and further to 90% with the aforementioned methods

Radar signal processing for sensing in assisted living: the challenges associated with real-time implementation of emerging algorithms

This article covers radar signal processing for sensing in the context of assisted living (AL). This is presented through three example applications: human activity recognition (HAR) for activities of daily living (ADL), respiratory disorders, and sleep stages (SSs) classification. The common challenge of classification is discussed within a framework of measurements/preprocessing, feature extraction, and classification algorithms for supervised learning. Then, the specific challenges of the three applications from a signal processing standpoint are detailed in their specific data processing and ad hoc classification strategies. Here, the focus is on recent trends in the field of activity recognition (multidomain, multimodal, and fusion), health-care applications based on vital signs (superresolution techniques), and comments related to outstanding challenges. Finally, this article explores challenges associated with the real-time implementation of signal processing/classification algorithms

Power consumption analysis of FPGA-based wireless communication systems

Les systèmes de communications sans fil n'ont cessé d'évoluer ces dernières années, poussés par de fortes demandes du marché en systèmes toujours plus autonomes et performants. Ainsi, de nouvelles contraintes de conception sont apparues de manière à mieux prendre en compte les aspects énergétiques et ainsi améliorer la durée de vie des batteries et des circuits. Actuellement, les systèmes de communications numériques sans fil consomment d'importantes quantités d'énergie. D'autre part, la complexité des systèmes croît de génération en génération afin de satisfaire toujours plus d'utilisateurs avec un haut niveau de performances. Dans ce contexte à fortes contraintes, les circuits de type FPGA apparaissent comme une technologie attractive, pouvant supporter des circuits numériques complexes grâce à leur grand nombre de ressources. Pour pouvoir concevoir les futurs systèmes de communications numériques sans fil sur ce type de circuit, les concepteurs de tels systèmes doivent pouvoir estimer la consommation et les performances au plus tôt dans la phase de conception. De cette façon, ils pourront explorer l'espace de conception et effectuer des choix d'implémentation afin d'optimiser leurs systèmes. Durant cette thèse, une méthodologie a été proposée dont les objectifs sont d'estimer rapidement et à haut niveau la consommation de leurs circuits implantés sur FPGA ainsi que leurs performances, d'explorer l'espace de conception, de comparer efficacement plusieurs systèmes entre eux, tout en assurant une bonne précision de l'estimation. La méthodologie repose sur une phase de caractérisation de composants IP matériels ainsi que de leur modélisation en Systeme. Dans un second temps, une représentation haut-niveau du système entier est réalisée à partir de la librairie des modèles Systeme de chaque IP. A travers des simulations haut-niveau, les utilisateurs peuvent tester rapidement de multiples configurations de leur système. Un des caractères innovants de l'approche repose sur l'utilisation de signaux clés qui permettent de tenir compte des comportements dynamiques des composants IP, c-à-d leur temps d'activité (actif/inactif), au sein du système et ainsi obtenir des estimations précises. Les nombreux gains de la méthodologie ont été démontrés à travers plusieurs exemples de systèmes de communications numériques sans fil comme une chaîne de traitement en bande de base de type SISO-OFDM générique, des émetteurs LTE etc. Pour conclure, les limitations ont été adressées et des solutions d'optimisation ont pu être envisagées puis mises en place.Wireless communication systems are still evolving since the last decades, driven by the growing demand of the electronic market for energy efficient and high performance devices. Thereby, new design constraints have appeared that aim at taking into account power consumption in order to improve battery-life of circuits. Current wireless communication systems commonly dissipate a lot of power. On the other hand, the complexity of such systems keeps on increasing through the generations to always satisfy more users at a high degree of performance. In this highly constrained context, FPGA devices seem to be an attractive technology, able to support complex systems thanks to their important number of resources. According to the FPGA nature, designers need to estimate the power consumption and the performance of their wireless communication systems as soon as possible in the design flow. In this way, they will be able to perform efficient design space exploration and make decisive implementation and optimization choices. Throughout this thesis, a power estimation methodology for hardware-focused FPGA device is described and aims at making design space exploration a lot easier, providing early and fast power and performance estimation at high-level. It also proposes an efficient way to efficiently compare several systems. The methodology is effective through an lP characterisation step and the development of their SystemC models. Then, a high level description of the entire system is realized from the SystemC models that have been previously developed. High-level simulations enable to check the functionality and evaluate the power and performance of the system. One of the contributions consists in monitoring the JP time-activities during the simulation. We show that this has an important impact on both power and performances. The effectiveness of the methodology has been demonstrated throughout several baseband processing chains of the wireless communication domain such as a SISO-OFDM generic chain, LTE transmitters etc. To conclude, the main limitations of the proposed methodology have been investigated and addressed

Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA

Wireless communication systems are still evolving since the last decades, driven by the growing demand of the electronic market for energy efficient and high performance devices. Thereby, new design constraints have appeared that aim at taking into account power consumption in order to improve battery-life of circuits. Current wireless communication systems commonly dissipate a lot of power. On the other hand, the complexity of such systems keeps on increasing through the generations to always satisfy more users at a high degree of performance. In this highly constrained context, FPGA devices seem to be an attractive technology, able to support complex systems thanks to their important number of resources. According to the FPGA nature, designers need to estimate the power consumption and the performance of their wireless communication systems as soon as possible in the design flow. In this way, they will be able to perform efficient design space exploration and make decisive implementation and optimization choices. Throughout this thesis, a power estimation methodology for hardware-focused FPGA device is described and aims at making design space exploration a lot easier, providing early and fast power and performance estimation at high-level. It also proposes an efficient way to efficiently compare several systems. The methodology is effective through an lP characterisation step and the development of their SystemC models. Then, a high level description of the entire system is realized from the SystemC models that have been previously developed. High-level simulations enable to check the functionality and evaluate the power and performance of the system. One of the contributions consists in monitoring the JP time-activities during the simulation. We show that this has an important impact on both power and performances. The effectiveness of the methodology has been demonstrated throughout several baseband processing chains of the wireless communication domain such as a SISO-OFDM generic chain, LTE transmitters etc. To conclude, the main limitations of the proposed methodology have been investigated and addressed.Les systèmes de communications sans fil n'ont cessé d'évoluer ces dernières années, poussés par de fortes demandes du marché en systèmes toujours plus autonomes et performants. Ainsi, de nouvelles contraintes de conception sont apparues de manière à mieux prendre en compte les aspects énergétiques et ainsi améliorer la durée de vie des batteries et des circuits. Actuellement, les systèmes de communications numériques sans fil consomment d'importantes quantités d'énergie. D'autre part, la complexité des systèmes croît de génération en génération afin de satisfaire toujours plus d'utilisateurs avec un haut niveau de performances. Dans ce contexte à fortes contraintes, les circuits de type FPGA apparaissent comme une technologie attractive, pouvant supporter des circuits numériques complexes grâce à leur grand nombre de ressources. Pour pouvoir concevoir les futurs systèmes de communications numériques sans fil sur ce type de circuit, les concepteurs de tels systèmes doivent pouvoir estimer la consommation et les performances au plus tôt dans la phase de conception. De cette façon, ils pourront explorer l'espace de conception et effectuer des choix d'implémentation afin d'optimiser leurs systèmes. Durant cette thèse, une méthodologie a été proposée dont les objectifs sont d'estimer rapidement et à haut niveau la consommation de leurs circuits implantés sur FPGA ainsi que leurs performances, d'explorer l'espace de conception, de comparer efficacement plusieurs systèmes entre eux, tout en assurant une bonne précision de l'estimation. La méthodologie repose sur une phase de caractérisation de composants IP matériels ainsi que de leur modélisation en Systeme. Dans un second temps, une représentation haut-niveau du système entier est réalisée à partir de la librairie des modèles Systeme de chaque IP. A travers des simulations haut-niveau, les utilisateurs peuvent tester rapidement de multiples configurations de leur système. Un des caractères innovants de l'approche repose sur l'utilisation de signaux clés qui permettent de tenir compte des comportements dynamiques des composants IP, c-à-d leur temps d'activité (actif/inactif), au sein du système et ainsi obtenir des estimations précises. Les nombreux gains de la méthodologie ont été démontrés à travers plusieurs exemples de systèmes de communications numériques sans fil comme une chaîne de traitement en bande de base de type SISO-OFDM générique, des émetteurs LTE etc. Pour conclure, les limitations ont été adressées et des solutions d'optimisation ont pu être envisagées puis mises en place

Consommation de puissance dynamique des systèmes de télécommunication sans fils sur FPGA

Séminaire des jeudis de la com' de l'équipe SCNLes systèmes de télécommunication actuels sont de plus en plus complexes. Ils délivrent un haut niveau de performances en termes de débit, vitesse de calcul au prix d'une importante consommation de puissance. Les contraintes sont d'autant plus fortes lorsqu'il faut embarquer le système. Pour les concepteurs de tels systèmes, être capable d'estimer la consommation de puissance au plus tôt dans le flot de conception est un élément déterminant. Après avoir analysé les origines de consommation de puissance dans les FPGAs, nous présentons la méthodologie développée, basée sur une utilisation conjointe de XPower Analyzer et de SystemC. La méthodologie se déroule en deux étapes, une phase de caractérisation individuelle de chaque bloc puis une seconde phase consistant à une simulation haut-niveau du système global. Comme exemple d'application, nous estimons la consommation de puissance dynamique de l'émetteur d'une chaîne SISO-OFDM suivant 3 scénarios utilisateurs. Nous obtenons une erreur absolue maximale de 4.767% qui démontre l'efficacité de la méthodologie proposée. En conclusion, la méthodologie permet d'obtenir des estimations relativement précises et très rapidement sans avoir à développer l'ensemble du système. Concernant les perspectives, nous souhaitons appliquer la méthodologie sur des systèmes MISO, MIMO dans les contextes LTE et WIMAX. De plus, nous définirons de nouvelles métriques de comparaison d'algorithmes intégrant la consommation de puissance (exemple : consommation de puissance, débit...

RF-NoC cognitif pour les architectures manycore

International audienceLe développement des architectures manycore avec des milliers de coeurs sur une même puce, révèle de nouveaux défis, notamment vis-à-vis des interconnex-ions entre coeurs ou groupe de coeurs. L'introduction d'interconnexion RF combiné avec l'OFDMA (Orthogo-nal Frequency-Division Multiple Access) s'avère une solution prometteuse. Dans ce résumé, nous présentons nos travaux préliminaires vers le développement d'une architecture RF-NoC cognitive visant à améliorer les communications au sein d'un RF-NoC. Pour cela, nous mod-élisons l'architecture et évaluons les performances d'un algorithme de routage adapté